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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:48:25 01/15/2010 
-- Design Name: 
-- Module Name:    demo - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Clk_200kHz is
	Port(FPGA_Clk : IN std_logic;
		   I2C_Clk : out std_logic;
		   I2C_Clk_X2 : out std_logic;
		   I2C_Clk_X4 : out std_logic);
end Clk_200kHz;

architecture Behavioral of Clk_200kHz is
	signal sI2C_Clk,sI2C_Clk_X2,sI2C_Clk_X4 : std_logic:='0';
	signal clk_div : std_logic_vector(7 downto 0):=(others=>'0');
begin
	
	I2C_Clk<=sI2C_Clk;
	I2C_Clk_X2<=sI2C_Clk_X2;
	
	process(FPGA_Clk)
	begin
		if rising_edge(FPGA_Clk) then
			if clk_div = X"7C" then
				sI2C_Clk<=not sI2C_Clk;
				sI2C_Clk_X2<=not sI2C_Clk_X2;
				sI2C_Clk_X4<=not sI2C_Clk_X4;
				clk_div<=(others=>'0');
			elsif clk_div = X"3E" then
			  sI2C_Clk_X2<=not sI2C_Clk_X2;
			  sI2C_Clk_X4<=not sI2C_Clk_X4;
			  clk_div<=clk_div+1;
			elsif clk_div = X"1F" or clk_div = X"5D" then
			  sI2C_Clk_X4<=not sI2C_Clk_X4;
			  clk_div<=clk_div+1;
			else
			  clk_div<=clk_div+1;
			end if;
		end if;
	end process;			

end Behavioral;

